The present invention relates to a circuit for generating pulse width modulation (PWM) signals, which is suitable for controlling an inverter.
As a conventional system for generating PWM signals, a system as shown in FIGS. 3(a)-3(d) is known, wherein a counter, which is preset to a carrier cycle for indicating a control cycle of PWM, operates to count down a signal as shown in FIG. 3(a), and a counter output UDC is compared with contents of registers storing two kinds of level information, i.e. a set level SL and a reset level RL. When the counter output UDC coincides with the set level SL, a set pulse SP is outputted as shown in FIG. 3(b) to turn on an PWM power OUT as shown in FIG. 3(d), and when the counter output UDC coincides with the reset level RL, a reset pulse RP is outputted as shown in FIG. 3(c) to turn off the PWM power OUT.
Namely, in the above system, it is required to calculate two points for the set level and the reset level in order to output a PWM waveform, which is generally calculated by CPU or a computer. However, in case a carrier cycle becomes short, the CPU is short of calculation time, so that the minimum value for the carrier cycle is determined by a calculation time of CPU.
Accordingly, an object of the invention is to provide a circuit for generating pulse width modulation signals, which operates to relieve load for CPU and to shorten the carrier cycle.